The present invention relates, in general, to electric circuits and, more particularly, to electric circuit support structures.
Semiconductor devices are typically manufactured from a semiconductor wafer. The wafer is diced to form chips or dice, which are mounted to a substrate such as a leadframe. Similarly, passive devices such as capacitors and resistors may be mounted to the leadframe. The devices are typically bonded to the leadframes using solder. FIG. 1 illustrates a device 116 bonded to portions 112 and 114 of a leadframe using solder 118. A drawback with this structure is that the solder may form bridges that short the terminals of the devices mounted to the leadframe, which results in failure of the electronic module.
Accordingly, it would be advantageous to have an electric circuit and a method for manufacturing the electric circuit that mitigates formation of bridges. It would be of further advantage for the electric circuit to be cost efficient to manufacture.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.